An analog-to-digital converter (ADC) converts an analog signal (e.g., voltage level) into a corresponding digital signal (e.g., binary word). There are numerous ways to implement an ADC. One type of ADC is a successive approximation register (SAR). A SAR is formed from a comparator and a digital-to-analog converter (DAC). At the start of the conversion cycle, the DAC is set to half scale and a comparison is made between the voltage input and output of the DAC. With each step, the DAC is updated, the next bit is selected, a subsequent comparison made, and the digital value found using a binary search (or “successive approximation”) technique.
Another conventional type of ADC is an incremental converter. An incremental converter utilizes an integrator and comparator and a pair of references. The input is integrated on one phase of the clock cycle. The reference is then integrated in the opposite direction in the second phase of the clock cycle. The reference selection, positive or negative, is driven by the comparator, always integrating back to zero. The number of cycles in which the comparator output is positive is then counted to obtain the digital result. This is algorithmically equivalent to a dual slope ADC. The incremental ADC makes 2n comparisons to form an n-bit conversion.
Yet another conventional type of ADC is a delta sigma ADC. The delta sigma ADC utilizes the same integrator/comparator topology as an incremental converter ADC. Rather than integrating the comparator output in a counter, the comparator result is processed in a decimator.
Such conventional ADCs utilize a fixed architecture. That is, a conventional ADC is not reconfigurable after fabrication. Conventional ADCs suffer from pre-selected tradeoffs made during fabrication.